1. Field of the Invention
The present invention relates to non-volatile semiconductor memory devices and, more specifically, to a non-volatile semiconductor memory device having an electrically rewritable non-volatile semiconductor as a memory element.
2. Description of the Background Art
In an EEPROM as an electrically rewritable non-volatile semiconductor memory device, a high voltage of 20 V is applied to a memory cell corresponding to a binary information in accordance with a writing mode signal applied from a controller, and threshold value of the memory cell is changed to receive charges, whereby the information is written. Methods for applying high voltage to the memory cell comprise a method of applying the voltage from a voltage source directly to an external terminal provided in each memory cell, and a method of applying a normal voltage 5 V which is boosted by a boosting circuits provided in an IC to apply the boosted voltage. One example of the latter method is disclosed in Japanese Patent Laying-Open No. 63-7599.
FIG. 4 is a block diagram showing a whole structure of a conventional EEPROM. Referring to FIG. 4, a clock pulse is applied to an input register 101 and data and address are serially input thereto. The input register 101 serially reads the data and the address in response to the clock pulse, loads the data in a data register 103 and loads the address through an address register/decoder 104. The clock pulse is also applied to a timing generation circuit 102, which generates timing signals in response to the clock pulse to apply the same to a mode register 105. The mode register 105 is provided for loading a writing mode signal or an erasing mode signal. The writing mode signal or the erasing mode signal loaded in the mode register 105 is applied to a control circuit 1.
The data loaded in the data register 103 and the address signal loaded in the address register/recorder 104 are applied to a memory cell 100. The writing mode signal is also applied to a boosting circuit 2 and a writing circuit 111. The boosting circuit 2 boost a supply voltage of +5 V to a high voltage of 20 V in response to the writing mode signal or the erasing mode signal to apply the same to the memory cell 100 through the writing circuit 111. When the high voltage is applied to a cell of the designated address, the memory cell 100 writes the information in the cell. A sensing circuit 101 amplifies the information read from the memory cell 100 to apply the same to an output circuit 109.
FIG. 5 is a specific block diagram of the memory cell portion shown in FIG. 4, FIG. 6 is a specific electric circuit diagram of the boosting circuit shown in FIG. 5, and FIG. 7 is a specific electric circuit diagram of a high voltage switch.
Referring to FIGS. 5 to 7, the portions near the memory cell will be described in more detail. FIG. 5 shows an example of a memory matrix MA in which memory cells M11 . . . M1n+1, M21 . . . M2n+1, M31 . . . M3n+1 M41 . . . M4n+1 arranged in a matrix of two columns.times.two rows for rewriting n bit data at one time. The memory cell M11 comprises a selective transistor and a memory transistor. Other memory cells have the same structure. The selective transistor of each of the memory cells M11 . . . M1n+1, M21 . . . M2n+1, M31 . . . M3n+1, M41 . . . M4+1 is connected to each other in the row direction by the word lines W1, W2, and in the column direction by digit lines D11 . . . 1, D21 . . . D2n+1. High voltage switches 71 and 72 are connected to the word lines W1 and W2, high voltage switches 52 . . . 5n+1 are connected to the digit lines D11 . . . , D1n+1 and high voltage switches 62 . . . 6n+1 are connected to the digit lines D21 . . . D2n+1. Transistors 81 and 82 transmit high voltage on a control gate line CG1 to the control gate of the memory cells M11 . . . M1n+1, M21 . . . M2n+1 and transistors 83 and 84 transmit high voltage on a control gate line CG2 to the control gates of the memory cells M31 . . . M3n+1, M41 . . . M4n+1. Drains of the transistors 81 and 82 are connected to the high voltage switch 51 and the drains of the transistors 83 and 84 are connected to the high voltage switch 61.
The control circuit 1 applies a controlling signal for generating a high voltage from the boosting circuits 2 in the writing mode and in the erasing mode to the boosting circuit 2. The boosting circuit 2 comprises an oscillator 21 as shown in FIG. 6. The oscillator 21 starts the oscillating operation in response to the controlling signal from the control circuit 1. The boosting circuit 2 comprises n channel transistors 23 connected in series with the gates and drains connected to each other and capacitors 24 connected between the source of each of the transistors 23 and the output of the oscillator 21 or an output of an inverter 22 inverting the output from the oscillator 21. The boosting circuit 2 is generally called a charge pump, which boost the output from the oscillator 21 by the combination of the N channel transistors 23 and the capacitor 24 to apply a high voltage to the high voltage switches 51, 52 . . . 5n+1, 61, 62 . . . 6n+1, 71 and 72.
The control circuit 1 applies a control signal in the writing mode and in the erasing mode to one input end of each of the NAND gates 31 and 41. An address signal Y1 is applied to the other input end of the AND gate 31, and an address signal Y2 is applied to the other input end of the NAND gate 41. Data D1 . . . Dn are applied to one input end of the AND gates 32 . . . 3n+1, respectively, and the address signal Y1 is applied to the other input end. The data D1 . . . Dn are applied to one input end of the AND gates 42 . . . 4n+1, respectively, and the address signal Y2 is applied to the other input end. Address signals X1 and X2 are applied to the high voltage switches 71 and 72.
Referring to FIG. 7, the structure of the high voltage switch 50 will be described in the following. An output from any one of the AND gates 31, 32 . . . 3n+1, 41, 42 . . . 4n+1 and X1, X2 shown in FIG. 5 is applied to the inverter 501. The output from the inverter 501 is applied to the gates of N channel transistor 502 which has its source connected to the ground and its drain connected to the drain of an N channel transistor 503 and to the gate of an N channel transistor 504. The gate and the source of the N channel transistor 503 are connected to one end of a capacitor 505 and to the source of the N channel transistor 504. A high voltage is applied from the boosting circuit 2 to the drain of the N channel transistor 504, while the oscillation output from the oscillator 21 is applied to the other end of the capacitor 505. A high voltage is output from the drain of the N channel transistor 502.
Operation of a conventional EEPROM will be described in the following. The high voltage switch 50 is a switching element for switching a high voltage (about 20 V) for writing into the EEPROM by peripheral 5 V signals. When a "H" level (5 V) signal is input to the gate of the N channel transistor 502, the N channel transistor 502 is turned on and a "L" level signal is output from the drain thereof. When a "L" level (0 V) signal is input to the gate of the N channel transistor 502, the N channel transistor 502 is turned off, and the capacitor 505, and N channel transistors 503 and 504 function as a last stage of the boosting circuit 2 to output a high voltage.
The operation of erasing and writing data in the memory cell M11 which is at the first row and first column of the 2.times.2 memory cell array MA shown in FIG. 5 will be described in the following as an example. The EEPROM has two modes, that is, the erasing mode and the writing mode. At first, the erasing mode will be described. The erasing of data is carried out by applying a high voltage of about 20 V to the gate (generally called as a control gate) of a memory transistor of the memory cell M11. A control signal for starting oscillation is applied from the control circuit 1 to the oscillator 21 of the boosting circuit 2. The oscillator 21 starts oscillation in response to the control signal and the boosting circuit 2 generates a high voltage. On this occasion, the control signal E output from the control circuit 1 is set to the "H" level, and the data D1 to Dn are set to the "L" level. Now, the information in the memory cell D11 at the first row and first column is to be erased, so that the address signal X1 is set to the "H" level, X2 is set to the "L" level, Y1 is set to the "H" level and Y2 is set to the "L" level. Consequently, the AND gate 31 conducts, the high voltage switch 51 sets the control gate signal CG1 at 20 V and the high voltage switch 71 such the word signal W1 at 20 V. Consequently, the transistor 81 is rendered conductive, a high voltage is applied to the control gate of the memory cell M11, whereby the data is erased.
Writing of the data is carried out by applying a high voltage of 20 V to the drain of a memory transistor in the memory cell. Namely, in the writing mode, the control signal E is set to the "L" level and the data D1 to Dn are set at respective values. The address signals X1, X2, Y1 and Y2 are set in the same manner as in the erasing mode. When the control gate signal CG1 is kept at the "L" level and the data D1 to Dn are at the "L" level, the high voltage is not transmitted to the digital signal D11, so that writing of data to the memory cell is not carried out. When the data D1, for example, is set at the "H" level, the high voltage is transmitted to the digit signal D11, so that writing of data to the memory cell M11 is carried out.
When the EEPROM shown in FIG. 5 is used as a memory element, there is a possibility of the data stored in the EEPROM being destroyed when the power supply is turned on/off or the applied voltage is stopped for an instant. More specifically, the power is supplied through an external terminal to the boosting circuit 2. When the high voltage is applied to the memory cell and the signal output from the controller becomes unstable due to the turning on/off the power supply or the instant stoppage, the memory device may be erroneously set to the writing mode. When a boosting circuit 2 such as shown in FIG. 6 is provided in the memory device and the signal output from the controller becomes unstable due to the turning on/off of the power supply or the instant stoppage, the writing mode may be erroneously set.
Electrical rewriting of data is possible in an EEPROM. However, in most cases, they are used as ROMs, that is, only a portion is used for writing data and other regions are used only for reading with the data once written being maintained as they are. Therefore, various measurements have been proposed in order to prevent fatal damage of the system derived from the destruction of the written data by the above described causes.
For example, measurements such as providing pull up and pull down resistances to an input terminal, provision of a power supply detecting circuit inside or outside of the IC so as to turn off the main power supply after the external signal lines are established, and so on have been proposed. However, these measurements are not enough to prevent erroneous writing.